Fully depleted, trench-pinned photo gate for CMOS image sensor applications

François Roy (1) , Andrej Suler (1) , Thomas Dalleau (1, 2) , Romain Duru (1) , Daniel Benoit (1) , Jihane Arnaud (1) , Yvon Cazaux (3) , Catherine Chaton (3) , Laurent Montes (4) , Panagiota Morfouli (4) , Guo-Neng Lu (2)

1 ST-CROLLES - STMicroelectronics [Crolles]
2 INL - CSH - INL - Conception de Systèmes Hétérogènes
3 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
4 IMEP-LAHC - Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation

Tackling issues of implantation-caused defects and contamination, this paper presents a new complementary metal–oxide–semiconductor (CMOS) image sensor (CIS) pixel design concept based on a native epitaxial layer for photon detection, charge storage, and charge transfer to the sensing node. To prove this concept, a backside illumination (BSI), p-type, 2-µm-pitch pixel was designed. It integrates a vertical pinned photo gate (PPG), a buried vertical transfer gate (TG), sidewall capacitive deep trench isolation (CDTI), and backside oxide–nitride–oxide (ONO) stack. The designed pixel was fabricated with variations of key parameters for optimization. Testing results showed the following achievements: 13,000 h+ full-well capacity with no lag for charge transfer, 80% quantum efficiency (QE) at 550-nm wavelength, 5 h+/s dark current at 60◦C, 2 h+ temporal noise floor, and 75 dB dynamic range. In comparison with conventional pixel design, the proposed concept could improve CIS performance.

Mots clés: Capacitive sensors; Charge transfer; CMOS integrated circuits; Dark currents; Digital cameras; Image sensors; Integrated circuit design; Passivation; Well testing; CMOS image sensor; Deep trench isolation; Photogates; Surface passivation; Transfer gate; Pixels

Domaines: Micro et nanotechnologies/Microélectronique

François Roy, Andrej Suler, Thomas Dalleau, Romain Duru, Daniel Benoit, et al.. Fully depleted, trench-pinned photo gate for CMOS image sensor applications. Sensors, 2020, 20 (3), pp.727. ⟨10.3390/s20030727⟩. ⟨hal-03770921⟩